Electronic devices often include logic and associated structures to facilitate testing. For example, devices can configure internal flip flops, latches, or registers into chains, called scan chains, for purposes of testing. These scan chains typically include the flip flops, latches, and/or registers that are utilized to support the normal operating logic of the devices. An electronic device that processes digital data can be scan tested by clocking a known sequence of data through the scan chains. If the internal processing and logic of the electronic device are valid and error-free, then the device will generate expected output sequence(s) or vector(s) in response to the test scan patterns. Scan testing can be used to test internal structures and logic elements that would be otherwise inaccessible. Scan testing, however, gives rise to data access issues that must be taken into consideration, especially in light of the encryption and security requirements of the software, telecommunications, entertainment, and other industries.
The author of an encryption algorithm (or other secret or proprietary function) may want to keep the algorithm secret. Protected algorithms might also be used as part of other proprietary data processing methods, e.g., filtering, data compression, digital signal processing, digital rights management, or the like. For example, an algorithm that utilizes a proprietary digital mapping or conversion scheme may be implemented by a hardware-based or memory-based lookup table, where the contents of the table are protected by appropriate confidentiality agreements. In practice, electronic devices on semiconductor chips are often utilized to execute proprietary algorithms. However, if the circuitry responsible for handling the secure codes and implementing proprietary processing logic is accessible via scan testing, competitors might be able to exploit the scanning procedure and use reverse engineering techniques to gain access to the secure codes, algorithms, or logic stored in the chip.